The SONET system is intended for implementing the electronic/photonic interface for fiber optic communication networks according to the new Synchronous Optical Network (SONET) Standard defined in ANSI Standard T1.105 etc. According to the SONET Standard, electronic signals are formatted in synchronous transport signal (STS) frames of 810 bytes with 125 .mu.S frame time period and base transmission rate of 51.840 Mb/s. The STS frames include the transport overhead bytes and a synchronous payload envelope (SPE) of data bytes combined in a standard frame format of 9 rows of bytes of 90 columns of bytes. The basic SONET STS-1 frame is constructed with three columns of transport overhead bytes as the first three columns followed by 87 columns of SPE data bytes. Each row is therefore composed of 3 transport overhead bytes and 87 data bytes. The SPE also includes one column of path overhead bytes.
Within each STS frame the synchronous payload envelope SPE may be composed of so called virtual tributaries (VT's), i.e., data structures from lower speed or lower frequency service networks. The VT's are packaged or multiplexed together in the synchronous payload envelopes of STS frames for high speed SONET transmission. Multiple STS frames can also be multiplexed together in a single STS-N frame structure.
Internationally, the SONET system is referred to as synchronous digital hierarchy or SDH. The basic SDH frame is similar to an STS-3 frame of 9 rows by 270 columns. The rows are divided into an initial 9 columns of transport overhead bytes followed by 261 columns of data bytes. Each row is therefore composed of 9 transport overhead bytes followed by 261 data bytes.
In summary, SONET ANSI T1 sets the standard for the formatting of data into frames of transport overhead bytes and data payload envelopes, the multiplexing of formatted data, processing of frames, scrambling of data for power modulation, and generally the data handling and management for interfacing electronic signals with optical carriers on fiber optic transmission networks.
Referring to FIG. 1, a typical pointer processor circuit consists of a pointer interpreter (PI), first in first out memory (FIFO) and a pointer generator (PG). The PI circuit receives an incoming frame, locates the pointer in the transport overhead bytes of the incoming frame identified as the H1H2 bytes, and interprets the pointer which points to and gives the location of the trace byte J1. J1 identifies the start of the synchronous payload envelope of data bytes for that incoming frame. The PI then writes the data bytes of the incoming frame to the FIFO.
The pointer generator constructs a new pointer H1H2 because generally the data payload envelope of data bytes will begin at a different location of the synchronous payload envelope in the outgoing frame compared to the incoming frame. The incoming and outgoing frames are independent of each other. The pointer generator circuit also reads the data bytes from the FIFO and begins constructing a new SONET frame as the outgoing frame.
The pointer processor of the present invention including the PI, FIFO, and PG is part of the overall SONET/SDH frame processing circuit. For example the PI is coupled on the upstream side to a frame detector circuit for detecting overhead bytes from the incoming frame. This circuit checks the incoming framing bytes A1A2 and other overhead bytes. Transport overhead bytes are extracted from the frame and parity bytes are checked.
The PG circuit is coupled to a multiplexing circuit or MUX followed by an overhead insertion circuit for restoring new transport overhead bytes to the outgoing frame. The multiplexer or MUX constructs the frame according to a STS-N formula, parity bits are inserted, and finally the bits are modulated by a feedback scrambler. It is noted that feedback scrambling is not for the purpose of encryption but for modulating power by distributing pulse signal edges.
The SONET STS frames themselves can be multiplexed into N frame structures. For example a 3 to 1 multiplexer will combine 3 STS-1 frames into a single STS-3 frame as illustrated in FIG. 1A. Synchronous multiplexing is achieved by interleaving bytes at corresponding locations of the respective STS frames after aligning the transport overhead bytes of the respective STS frames. A multiplexed STS-N frame has the same frame time period of 125.mu.S as an STS-1 frame. The SONET Standard accommodates byte interleaved synchronous multiplexing STS-N of at least 48 STS frames. An STS-48 frame results in SONET Signal transmission rates in the 2 gHz range (e.g. 48.times.51.840 Mb/s).
During pointer processing, writing data bytes in the FIFO, and reading data bytes from the FIFO, several events may require justification by the pointer processor between the outgoing frame and the incoming frame. Justification is required if the incoming frame rate is slightly different from the outgoing frame rate, i.e. if the PI clock and PG clock differ. Justification is required if a data byte is previously written in the transport overhead byte location H3. Justification is also required if a dummy byte, stuff byte, or blank byte is written in the data byte location following the H3 location. Location H3 is designated the negative justification data holding byte location.
If PICLK&gt;PGCLK, an extra data byte coming in is written from the FIFO into the H3 location of the outgoing frame in a negative justification or decrement step. Or a data byte may have been previously written in the H3 location of the incoming frame. It is then used for a negative decrement or negative justification.
If PICLK&lt;PGCLK so that the outgoing frame takes away more bytes than are supplied by the incoming frame, a positive justification or increment is required. The PG writes a dummy byte or blank byte in the outgoing frame at the data byte location following H3. The PG will therefore leave an empty data byte location following H3 to compensate for the shortage of data bytes arriving. Or a previous stage may have written a dummy byte or empty byte in the data byte location following H3. This would prompt a positive justification step or positive increment.
The pointer gap problem arises during justification of the incoming and outgoing frames. Suppose the incoming frame clock (PICLK) is slightly faster than the outgoing frame clock (PGCLK) so that a negative justification or decrement is required every 30 frames. The pointer processor circuit proceeds methodically through each frame and every 30 frames a threshold is crossed that prompts the negative justification. With respect to a particular row of the outgoing frame, the pointer processor circuit shifts one byte every 30 frames. Therefore after 90.times.30=2700 frames, the pointer processor has stepped along an entire row of the outgoing frames. While stepping through the 87 data bytes of a row, a threshold is crossed and a justification occurs regularly every 30 frames. However upon reaching the three transport overhead bytes, no bytes are written into the FIFO and therefore no justification occurs. The pointer processor therefore steps through 120 frames without any justification occurring.
This gap in the justifications is called the pointer justification gap or pointer gap. The pointer gap problem causes havoc in the desynchronizers that respond and adapt to the fixed offset of 30 frames established by 87 data bytes of the row. By way of a specific example, reference is made to FIG. 2. FIG. 2 illustrates an incoming SONET frame and an outgoing SONET frame. The first three columns on the left represent transport overhead bytes while 87 columns to the right represent data bytes of the payload envelope.
A possible scenario is at time T (this time is relative to start of outgoing frame) byte B84 is being written to the FIFO while byte D5 is being read from the FIFO. Assuming that the FIFO is filled to Z number of byte initially, then for identically incoming and outgoing frame rates, the FIFO at time T will always have Z bytes even though when the incoming row of the frame is at the overhead positions, the FIFO will be down to (Z-3) bytes and when the outgoing frame is at the overhead positions the FIFO will climb back up to Z bytes.
Now assuming the incoming frame rate is faster than the outgoing frame rate, then there would come a time when at time T, B85 byte would be written to the FIFO instead of B84 byte. This would cause the FIFO to have (Z+1) bytes at time T. At the next opportunity, a pointer justification would occur wherein a slot in the outgoing frame where an overhead typically goes, a data byte would be read from the FIFO. Because of this, at time T in the next frame, there would be Z bytes in the FIFO again.
Some time later, the situation would occur when at time T, B86 would be written to the FIFO instead of B85. The FIFO would have (Z+1) bytes and another justification would occur which would bring the FIFO at time T to Z bytes. If the time difference between the first justification and the second is time X, then when the time comes for B87 to cause a pointer justification, that justification occurs exactly X time units later.
After some time, E1 byte wants to be written to the FIFO but E1 byte is an overhead byte and thus does not get written. So X time units later, the FIFO at time T is still at Z bytes and a justification does not occur. Similarly E2 and E3 overhead bytes do not cause justifications for 2X time units.
Then F1 gets written to the FIFO which causes the FIFO at time T to have (Z+1) bytes and causes a justification. Henceforth the justifications occurs periodically spaced at X time units apart. This, in a nutshell, is the pointer justification gap problem.
One way of avoiding the problem is to use a high frequency clock and write the 87 bytes of data from each row of the incoming SONET/SDH frame in the FIFO evenly over the 90 byte time slots that exist in a row. That is, each byte is not written when it occurs, but is delayed a small time interval (3/87 of a byte time) on the input side of the pointer processor and FIFO. The disadvantage to this method is that one usually does not have a high speed clock or that the technology used to implement the function does not allow one to use such a high frequency clock, for example a 155 MHz clock in CMOS technology.